High-Speed Multioperand Decimal Adders

High Speed Decimal Addition

Parallel decimal arithmetic capability is becoming increasingly attractive with new applications of computers in a multiprogramming environment. The direct production of decimal sums offers a significant improvement in addition over methods requiring decimal correction. These techniques are illustrated in the eight-digit adder which appears in the System/360 Model 195.

Design Alternatives for Parallel Saturating Multioperand Adders

Parallel saturating multioperand adders significantly improve the performance of GSM speech coders by giving compilers and assembly language programmers the ability to parallelize loops containing saturating dot products, while maintaining GSM compliant results. This paper presents four designs for parallel saturating multioperand adders. These designs have at most one carry-propagate adder on ...

Fast Signed-Digit Multi-operand Decimal Adders

Decimal arithmetic is desirable for high precision requirements of many financial, industrial and scientific applications. Furthermore, hardware support for decimal arithmetic has gained momentum with IEEE 7542008, which standardized decimal floating-point. This paper presents a new architecture for two operand and multi-operand signed-digit decimal addition. Signed-digit architectures are adva...

Design of residue generators and multioperand modular adders using carry-save adders

Residue generator is an essential building block of encoding/decoding circuitry for arithmetic error detecting codes and binary-to-residue number system (RNS) converter. In either case, a residue generator is an overhead for a system and as such it should be built with minimum amount of hardware and should not compromise the speed of a system. Multioperand modular adder (MOMA) is a computationa...

High Speed Power Efficient Asynchronous Adders